The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2014

Filed:

Mar. 16, 2012
Applicants:

Wan-lan Chiang, Taipei, TW;

Kuang Hann Lin, Taipei, TW;

Chih-ping Peng, Taipei, TW;

Inventors:

Wan-Lan Chiang, Taipei, TW;

Kuang Hann Lin, Taipei, TW;

Chih-Ping Peng, Taipei, TW;

Assignee:

Vishay General Semiconductor LLC, Hauppauge, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 23/10 (2006.01); H01L 21/00 (2006.01); H01L 23/40 (2006.01); H01L 23/367 (2006.01); H01L 23/433 (2006.01); H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 23/4093 (2013.01); H01L 2224/32245 (2013.01); H01L 2924/12044 (2013.01); H01L 23/49562 (2013.01); H01L 2924/10253 (2013.01); H01L 23/4334 (2013.01); H01L 2224/26175 (2013.01); H01L 2224/33181 (2013.01);
Abstract

A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.


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