The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2014
Filed:
Nov. 20, 2012
Analog Devices, Inc., Norwood, MA (US);
David J Clarke, Patrickswell, IE;
Javier Alejandro Salcedo, North Billerica, MA (US);
Brian B Moane, Raheen, IE;
Juan Luo, San Jose, CA (US);
Seamus Murnane, Bruff, IE;
Kieran K Heffernan, Patrickswell, IE;
John Twomey, Fountainstown, IE;
Stephen Denis Heffernan, Tipperary, IE;
Gavin Patrick Cosgrave, Wexford, IE;
Analog Devices, Inc., Norwood, MA (US);
Abstract
Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.