The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2014

Filed:

Dec. 24, 2010
Applicants:

Jin Lin, San Jose, CA (US);

Nishkam Ravi, Princeton, NJ (US);

Xinmin Tian, Union City, CA (US);

John L. NG, San Jose, CA (US);

Renat V. Valiullin, Novosibirsk, RU;

Inventors:

Jin Lin, San Jose, CA (US);

Nishkam Ravi, Princeton, NJ (US);

Xinmin Tian, Union City, CA (US);

John L. Ng, San Jose, CA (US);

Renat V. Valiullin, Novosibirsk, RU;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatus to provide loop parallelization based on loop splitting and/or index array are described. In one embodiment, one or more split loops, corresponding to an original loop, are generated based on the mis-speculation information. In another embodiment, a plurality of subloops are generated from an original loop based on an index array. Other embodiments are also described.


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