The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2014

Filed:

Jun. 21, 2012
Applicants:

Yogesh B. Wakchaure, Folsom, CA (US);

Kiran Pangal, Fremont, CA (US);

Xin Guo, San Jose, CA (US);

Qingru Meng, San Jose, CA (US);

Hanmant Belgal, El Dorado Hills, CA (US);

Inventors:

Yogesh B. Wakchaure, Folsom, CA (US);

Kiran Pangal, Fremont, CA (US);

Xin Guo, San Jose, CA (US);

Qingru Meng, San Jose, CA (US);

Hanmant Belgal, El Dorado Hills, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/16 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G11C 16/10 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); H01L 27/115 (2013.01);
Abstract

A memory device may include two or more memory cells in an integrated circuit, at least one flash cell acting as a select gate coupled to the two or more memory cells, and an interface to accept a select gate erase command and a select gate program command during normal operation of the integrated circuit. The integrated circuit may be capable to perform operations to erase the at least one select gate in response to the select gate erase command, and program the at least one select gate in response to the select gate program command.


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