The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2014

Filed:

Jul. 27, 2012
Applicants:

Timothy J. Dalton, Ridgefield, CT (US);

Ebenezer E. Eshun, Newburgh, NY (US);

Sarah L. Grunow, Poughkeepsie, NY (US);

Zhong-xiang He, Essex Junction, VT (US);

Anthony K. Stamper, Williston, VT (US);

Inventors:

Timothy J. Dalton, Ridgefield, CT (US);

Ebenezer E. Eshun, Newburgh, NY (US);

Sarah L. Grunow, Poughkeepsie, NY (US);

Zhong-Xiang He, Essex Junction, VT (US);

Anthony K. Stamper, Williston, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.


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