The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 29, 2014
Filed:
Oct. 25, 2010
Ho-chul Ji, Yongin-si, KR;
Ki-nam Kim, Seoul, KR;
Yong-woo Hyung, Yongin-si, KR;
Kyoung-won NA, Seoul, KR;
Kyoung-ho Ha, Seoul, KR;
Yoon-dong Park, Yongin-si, KR;
Dae-lok Bae, Seoul, KR;
Jin-kwon Bok, Suwon-si, KR;
Pil-kyu Kang, Anyang-si, KR;
Sung-dong Suh, Seoul, KR;
Seong-gu Kim, Pyeongtaek-si, KR;
Dong-jae Shin, Seoul, KR;
In-sung Joe, Seoul, KR;
Ho-chul Ji, Yongin-si, KR;
Ki-nam Kim, Seoul, KR;
Yong-woo Hyung, Yongin-si, KR;
Kyoung-won Na, Seoul, KR;
Kyoung-ho Ha, Seoul, KR;
Yoon-dong Park, Yongin-si, KR;
Dae-lok Bae, Seoul, KR;
Jin-kwon Bok, Suwon-si, KR;
Pil-kyu Kang, Anyang-si, KR;
Sung-dong Suh, Seoul, KR;
Seong-gu Kim, Pyeongtaek-si, KR;
Dong-jae Shin, Seoul, KR;
In-sung Joe, Seoul, KR;
Abstract
Optical waveguide and coupler devices and methods include a trench formed in a bulk semiconductor substrate, for example, a bulk silicon substrate. A bottom cladding layer is formed in the trench, and a core region is formed on the bottom cladding layer. A reflective element, such as a distributed Bragg reflector can be formed under the coupler device and/or the waveguide device. Because the optical devices are integrated in a bulk substrate, they can be readily integrated with other devices on a chip or die in accordance with silicon photonics technology. Specifically, for example, the optical devices can be integrated in a DRAM memory circuit chip die.