The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8789060 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 22, 2014

Filed:

Dec. 27, 2007
Applicants:

Ken Wadland, Grafton, MA (US);

Charles W. Grant, Leominster, MA (US);

Randall Lawson, Westford, MA (US);

Richard Allen Woodward, Jr., San Diego, CA (US);

Sean Bergan, Andover, MA (US);

Inventors:

Ken Wadland, Grafton, MA (US);

Charles W. Grant, Leominster, MA (US);

Randall Lawson, Westford, MA (US);

Richard Allen Woodward, Jr., San Diego, CA (US);

Sean Bergan, Andover, MA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 13/00 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method, computer program product and apparatus for utilizing simulated locking prior to starting concurrent execution are disclosed. The results of this simulated locking are used to define a canonical ordering which controls the order of execution and the degree of parallelism that can be used.


Find Patent Forward Citations

Wadland, Ken. (2014). Deterministic, parallel execution with overlapping regions (U.S. Patent No. 8789060). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8789060

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