The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2014
Filed:
Jun. 14, 2012
Ekaterina M. Ambroladze, Wappingers Falls, NY (US);
Michael A. Blake, Wappingers Falls, NY (US);
Michael Fee, Cold Spring, NY (US);
Hieu T. Huynh, Austin, TX (US);
Patrick J. Meaney, Poughkeepsie, NY (US);
Arthur J. O'neill, Poughkeepsie, NY (US);
Ekaterina M. Ambroladze, Wappingers Falls, NY (US);
Michael A. Blake, Wappingers Falls, NY (US);
Michael Fee, Cold Spring, NY (US);
Hieu T. Huynh, Austin, TX (US);
Patrick J. Meaney, Poughkeepsie, NY (US);
Arthur J. O'Neill, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.