The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2014

Filed:

Jan. 26, 2012
Applicants:

Chia-sheng Lin, Zhongli, TW;

Tzu-hsiang Hung, Kaohsiung, TW;

Inventors:

Chia-Sheng Lin, Zhongli, TW;

Tzu-Hsiang Hung, Kaohsiung, TW;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/44 (2006.01); H01L 23/60 (2006.01); H01L 23/522 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 2224/05548 (2013.01); H01L 23/60 (2013.01); H01L 23/522 (2013.01); H01L 23/3157 (2013.01); H01L 2224/02372 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/13024 (2013.01); H01L 23/481 (2013.01); H01L 2224/02377 (2013.01);
Abstract

An embodiment of the invention provides a chip package which includes: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; and a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers the entire side terminals of the signal conducting layer and partially covers the ground conducting layer such that a side terminal of the ground conducting layer is exposed on a side of the substrate.


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