The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2014
Filed:
Feb. 28, 2011
Applicants:
Sang-wook Park, Hwaseong-si, KR;
Nam-seog Kim, Yongin-si, KR;
Seung-duk Baek, Hwaseong-si, KR;
Inventors:
Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/02 (2013.01); H01L 2924/01005 (2013.01); H01L 24/05 (2013.01); H01L 2924/01033 (2013.01); H01L 2224/05548 (2013.01); H01L 2924/01006 (2013.01); H01L 2224/13022 (2013.01); H01L 2924/01047 (2013.01); H01L 2224/0236 (2013.01); H01L 2224/05012 (2013.01); H01L 2924/01322 (2013.01); H01L 23/3192 (2013.01); H01L 2224/13021 (2013.01); H01L 24/13 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/014 (2013.01); H01L 2224/024 (2013.01);
Abstract
In one embodiment, a wafer level package includes a rerouting pattern formed on a semiconductor substrate and a first encapsulant pattern overlying the rerouting pattern. The first encapsulant pattern has a via hole to expose a portion of the rerouting pattern. The package additionally includes an external connection terminal formed on the exposed portion of the rerouting pattern. An upper section of the sidewall and a sidewall of the external connection terminal may be separated by a gap distance. The gap distance may increase toward an upper surface of the encapsulant pattern.