The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8775983 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 08, 2014

Filed:

Dec. 21, 2012
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventor:

Xiaojun Wang, Cary, NC (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Some embodiments of the invention provide a method for identifying and displaying odd loops and hints for resolution of the odd loops in an IC design layout for printing on multiple masks. The method of some embodiments identifies the hints by evaluating the effectiveness and feasibility of different potential resolutions, ensuring that hints do not create additional odd loops. The method of some embodiments also displays indications of the odd loops and the hints which a user can use to troubleshoot an odd loop violation. The method of some embodiments also prioritizes or scores the resolution hints to facilitate efficient troubleshooting of odd loop violations.


Find Patent Forward Citations

Wang, Xiaojun. (2014). Layout fixing guideline system for double patterning odd cycle violations (U.S. Patent No. 8775983). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8775983

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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