The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2014
Filed:
Aug. 28, 2012
Xiao-hui Song, Xuchang, CN;
Yong Wei, Xuchang, CN;
Fu-sheng LI, Xuchang, CN;
Quan-sheng Cui, Xuchang, CN;
Jun-feng Di, Xuchang, CN;
Jun-gang LI, Xuchang, CN;
Yun-zhao Zheng, Xuchang, CN;
Hong-guang Shi, Xuchang, CN;
Tuo-fu Zheng, Xuchang, CN;
Yi-ding Song, Xuchang, CN;
Bao-shan Zhang, Xuchang, CN;
Xiao-hui Song, Xuchang, CN;
Yong Wei, Xuchang, CN;
Fu-sheng Li, Xuchang, CN;
Quan-sheng Cui, Xuchang, CN;
Jun-feng Di, Xuchang, CN;
Jun-gang Li, Xuchang, CN;
Yun-zhao Zheng, Xuchang, CN;
Hong-guang Shi, Xuchang, CN;
Tuo-fu Zheng, Xuchang, CN;
Yi-ding Song, Xuchang, CN;
Bao-shan Zhang, Xuchang, CN;
Xu Ji Group Corporation, Henan, CN;
State Grid Corporation of China, Beijing, CN;
Abstract
The present invention relates to an IEEE1588 protocol negative testing method, comprises steps of: connecting a IEEE1588 tester and a slave clock DUT to establish a real-time closed-loop feedback mechanism; taking the IEEE1588 tester as a master clock, and establishing a stable time synchronization with the slave clock DUT; obtaining the timing offset or path delay of the slave clock DUT before disturbance; assembling an abnormal message in a frame and sending it to the slave clock DUT; calculating the timing offset or path delay increment after disturbance of the abnormal message; determining whether there is a sudden change in the timing offset or path delay of the slave clock DUT, wherein if there is no sudden change, the test passes; otherwise the test fails. This testing method uses the field of correction field (correction Field) in the IEEE1588 message to 'magnify' the response of the slave clock DUT to the abnormal message stimulus, and realizes a real-time closed-loop detection to efficiently verify whether the message processing logic of the slave clock DUT follows the IEEE1588 protocol.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile