The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2014

Filed:

Jul. 31, 2012
Applicants:

Karl J. Duvalsaint, Lagrangeville, NY (US);

Harm P. Hofstee, Austin, TX (US);

Daeik Kim, Beacon, NY (US);

Moon J. Kim, Wappingers Falls, NY (US);

Inventors:

Karl J. Duvalsaint, Lagrangeville, NY (US);

Harm P. Hofstee, Austin, TX (US);

Daeik Kim, Beacon, NY (US);

Moon J. Kim, Wappingers Falls, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/00 (2006.01); G06F 7/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.


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