The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2014
Filed:
Mar. 15, 2013
Samsung Electronics Co., Ltd., Suwon-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, KR;
Abstract
A duty cycle error accumulation circuit includes first to nth delay units and a feedback unit. The first to nth delay units receive a clock signal, a first input signal and a second input signal, respectively, to generate a first output signal and a second output signal by delaying one signal selected from first and second input signals based on a logic level of the clock signal. The feedback unit supplies second input signal to a kth delay unit based on second output signal of a (k+1)th delay unit. The first output signal of the kth delay unit is supplied to the (k+1)th delay unit as first input signal, and the clock signal is supplied to the first delay unit as first input signal and to the nth delay unit as second input signal. The duty cycle error accumulation circuit effectively corrects a duty cycle of a clock signal.