The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2014
Filed:
Jan. 17, 2013
Chan-hong Chern, Palo Alto, CA (US);
Tzu-ching Chang, Dali, TW;
Min-shueh Yuan, Taipei, TW;
Yuwen Swei, Fremont, CA (US);
Chih-chang Lin, San Jose, CA (US);
Chiang Pu, San Jose, CA (US);
Ming-chieh Huang, San Jose, CA (US);
Kuoyuan Hsu, San Jose, CA (US);
Chan-Hong Chern, Palo Alto, CA (US);
Tzu-Ching Chang, Dali, TW;
Min-Shueh Yuan, Taipei, TW;
Yuwen Swei, Fremont, CA (US);
Chih-Chang Lin, San Jose, CA (US);
Chiang Pu, San Jose, CA (US);
Ming-Chieh Huang, San Jose, CA (US);
Kuoyuan Hsu, San Jose, CA (US);
Abstract
A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.