The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2014

Filed:

Aug. 30, 2011
Applicants:

Sukhun Choi, Suwon-si, KR;

Boun Yoon, Seoul, KR;

Kevin Ahn, Hwaseong-si, KR;

Doo-sung Yun, Suwon-si, KR;

Inventors:

Sukhun Choi, Suwon-si, KR;

Boun Yoon, Seoul, KR;

Kevin Ahn, Hwaseong-si, KR;

Doo-Sung Yun, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 47/00 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2409 (2013.01); H01L 27/2463 (2013.01); H01L 27/2481 (2013.01); H01L 45/06 (2013.01);
Abstract

According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening formed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.


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