The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2014
Filed:
Oct. 30, 2009
Wern-jieh Sun, Cupertino, CA (US);
Haichun Chun, Sunnyvale, CA (US);
Ernst W. Mayer, Cupertino, CA (US);
Greg Woolhiser, San Jose, CA (US);
Kuldeep Karlcut, Cupertino, CA (US);
Wern-Jieh Sun, Cupertino, CA (US);
Haichun Chun, Sunnyvale, CA (US);
Ernst W. Mayer, Cupertino, CA (US);
Greg Woolhiser, San Jose, CA (US);
Kuldeep Karlcut, Cupertino, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
Some embodiments provide a system that facilitates the creation of a layout from a schematic in an electronic design automation (EDA) application. During operation, the system performs a tiered comparison of the schematic and the layout. The tiered comparison includes a first tier that compares labels in the schematic and the layout. The tiered comparison also includes a second tier that compares first-level connectivity in the schematic and the layout. The tiered comparison further includes a third tier that determines a graph isomorphism between the schematic and the layout. After the tiered comparison is completed, the system provides a result of the tiered comparison to a user of the EDA application. Finally, the system enables repairs of mismatches in the result by the user through a graphical user interface (GUI) associated with the EDA application.