The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2014

Filed:

Jun. 29, 2007
Applicants:

Dave Stuttard, Bristol, GB;

Dave Williams, Emerson Green, GB;

Eamon O'dea, Bristol, GB;

Gordon Faulds, Dursley, GB;

John Rhoades, Durham, NC (US);

Ken Cameron, Bristol, GB;

Phil Atkin, Slough, GB;

Paul Winser, Bristol, GB;

Russell David, Wootton Bassett, GB;

Ray Mcconnell, Clifton, GB;

Tim Day, Edinburgh, GB;

Trey Greer, Chapel Hill, NC (US);

Inventors:

Dave Stuttard, Bristol, GB;

Dave Williams, Emerson Green, GB;

Eamon O'Dea, Bristol, GB;

Gordon Faulds, Dursley, GB;

John Rhoades, Durham, NC (US);

Ken Cameron, Bristol, GB;

Phil Atkin, Slough, GB;

Paul Winser, Bristol, GB;

Russell David, Wootton Bassett, GB;

Ray McConnell, Clifton, GB;

Tim Day, Edinburgh, GB;

Trey Greer, Chapel Hill, NC (US);

Assignee:

Rambus Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/312 (2006.01); G06F 13/16 (2006.01); G06F 12/00 (2006.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
Abstract

A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another. A data transfer controller is provided which is operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array.


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