The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2014
Filed:
Aug. 05, 2008
Po-lin Chen, Hsin-Chu, TW;
Kuo-yuan Tu, Hsin-Chu, TW;
Wen-ching Tsai, Hsin-Chu, TW;
Chun-nan Lin, Hsin-Chu, TW;
Shu-feng Wu, Hsin-Chu, TW;
Po-Lin Chen, Hsin-Chu, TW;
Kuo-Yuan Tu, Hsin-Chu, TW;
Wen-Ching Tsai, Hsin-Chu, TW;
Chun-Nan Lin, Hsin-Chu, TW;
Shu-Feng Wu, Hsin-Chu, TW;
Au Optronics Corporation, Hsin-Chu, TW;
Abstract
A thin-film transistor (TFT) includes a gate electrode, a gate dielectric layer, a semiconductor layer, source/drain electrodes, a passivation layer and a protection layer. The gate electrode is disposed on a substrate. The gate dielectric layer covers the gate electrode and the substrate. The semiconductor layer is disposed on the gate dielectric layer and above the gate electrode. The semiconductor layer has a channel region disposed above the gate electrode and source/drain regions disposed at both sides of the channel region. The source/drain electrodes are disposed on the source/drain regions of the semiconductor layer and each has a barrier layer disposed on the source/drain regions of the semiconductor layer and a conductive layer disposed on the barrier layer. The passivation layer is disposed over the surface of the source/drain electrodes. The protection layer is disposed over the substrate, the passivation layer, and the channel region of the semiconductor layer.