The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2014

Filed:

Sep. 22, 2011
Applicants:

Yij Chieh Chu, New Taipei, TW;

Yun-zong Tian, Taichung, TW;

Inventors:

Yij Chieh Chu, New Taipei, TW;

Yun-Zong Tian, Taichung, TW;

Assignee:

Inotera Memories, Inc., Taoyuan County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 19/00 (2011.01); H01L 21/66 (2006.01); G06T 7/00 (2006.01);
U.S. Cl.
CPC ...
G06F 19/00 (2013.01); H01L 22/20 (2013.01); H01L 22/14 (2013.01); H01L 22/12 (2013.01); G06T 7/001 (2013.01); G06T 2207/30148 (2013.01);
Abstract

A fault detection method of semiconductor manufacturing processes is disclosed. The method includes the steps of providing a storage device, collecting a fault detection and classification(FDC) parameter by the storage device, setting up a measurement site for measuring an online measurement parameter, collecting a wafer acceptance test(WAT) in correspondence to the FDC parameter, establishing a first relationship equation between the FDC parameter and the online measurement parameter, establishing a second relationship equation of the online measurement parameter and the WAT by using the first relationship equation, establishing a third relationship equation between the FDC parameter and the WAT, establishing a waning region of the manufacturing processes by using the first, second, and third relationship equations, and determining the situation of generating wafer defects according to the warning region. The present invention discloses a system architecture for the method.


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