The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2014
Filed:
Jan. 18, 2011
Bin Xie, Hong Kong, HK;
Pui Chung Simon Law, Hong Kong, HK;
Yat Kit Tsui, Hong Kong, HK;
Hong Kong Applied Science and Technology Research Institute Company Limited, Hong Kong Science Park, Shatin, New Territories, Hong Kong, CN;
Abstract
The present invention provides a method for forming a three-dimensional wafer stack having a single metallized stack via with a variable cross-sectional shape. The method uses at least first and silicon wafers. Each wafer has one or more integrated circuits formed thereon. One or more through-vias are formed in each silicon wafer followed by oxide formation on at least an upper and lower surface of the silicon wafer. The wafers are aligned such that each wafer through via is aligned with a corresponding through via in adjacent stacked wafers. Wafers are bonded to form a three-dimensional wafer stack having one or more stack vias formed from the alignment of individual wafer vias. Via metallization is performed by depositing a seed layer in each of the stack vias followed by copper electroplating to form a continuous and homogeneous metallization path through the three-dimensional wafer stack.