The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8754337 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 17, 2014

Filed:

Mar. 26, 2010
Applicant:

Kenichi Kaneda, Tokyo, JP;

Inventor:

Kenichi Kaneda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/03 (2006.01);
U.S. Cl.
CPC ...
Abstract

An object of the invention is to provide a method for fabricating a printed wiring board that can suppress warping of the printed wiring board and can improve the yield of semiconductor chip mounting and enhance the reliability of a semiconductor package. The printed wiring board fabrication method according to the invention is a method for fabricating a printed wiring board having a through-hole in a core layer, wherein the printed wiring board fabrication method includes the step of applying a laser from one side of the core layer to a position where the through-hole is to be formed in the core layer and the step of applying a laser to the same position from the opposite side of the core layer.


Find Patent Forward Citations

Kaneda, Kenichi. (2014). Printed wiring board fabrication method, printed wiring board, multilayer printed wiring board, and semiconductor package (U.S. Patent No. 8754337). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8754337

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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