The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2014
Filed:
Mar. 29, 2012
Yung-fa Lin, Hsinchu, TW;
Shou-yi Hsu, Hsinchu County, TW;
Meng-wei Wu, Hsinchu, TW;
Main-gwo Chen, Hsinchu County, TW;
Chia-hao Chang, Hsinchu, TW;
Chia-wei Chen, Taipei, TW;
Yung-Fa Lin, Hsinchu, TW;
Shou-Yi Hsu, Hsinchu County, TW;
Meng-Wei Wu, Hsinchu, TW;
Main-Gwo Chen, Hsinchu County, TW;
Chia-Hao Chang, Hsinchu, TW;
Chia-Wei Chen, Taipei, TW;
Anpec Electronics Corporation, Hsinchu Science Park, Hsin-Chu, TW;
Abstract
A super junction transistor includes a drain substrate, an epitaxial layer, wherein the epitaxial layer is disposed on the drain substrate, a plurality of gate structure units embedded on the surface of the epitaxial layer, a plurality of trenches disposed in the epitaxial layer between the drain substrate and the gate structure units, a buffer layer in direct contact with the inner surface of the trenches, a plurality of body diffusion regions with a first conductivity type adjacent to the outer surface of the trenches, wherein there is at least a PN junction on the interface between the body diffusion region and the epitaxial layer, and a doped source region, wherein the doped source region is disposed in the epitaxial layer and is adjacent to the gate structure unit.