The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2014

Filed:

Dec. 29, 2009
Applicants:

Jeong Woo Lee, Ichon-si, KR;

Hyung Dong Lee, Ichon-si, KR;

Jun Gi Choi, Ichon-si, KR;

Sang Hoon Shin, Ichon-si, KR;

Xiang Hua Cui, Ichon-si, KR;

Inventors:

Jeong Woo Lee, Ichon-si, KR;

Hyung Dong Lee, Ichon-si, KR;

Jun Gi Choi, Ichon-si, KR;

Sang Hoon Shin, Ichon-si, KR;

Xiang Hua Cui, Ichon-si, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor integrated circuit includes a multi-chip package having a plurality of semiconductor chips. The semiconductor integrated circuit includes a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal. Here, the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line.


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