The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2014

Filed:

Jul. 11, 2012
Applicants:

Honggun Kim, Hwaseong-si, KR;

Byeongju Bae, Hwaseong-si, KR;

Seung-heon Lee, Seoul, KR;

Mansug Kang, Suwon-si, KR;

Eunkee Hong, Seongnam-si, KR;

Inventors:

Honggun Kim, Hwaseong-si, KR;

ByeongJu Bae, Hwaseong-si, KR;

Seung-Heon Lee, Seoul, KR;

Mansug Kang, Suwon-si, KR;

Eunkee Hong, Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/02164 (2013.01);
Abstract

In a method of fabricating a semiconductor device, isolation structures are formed in a substrate to define active regions. Conductive structures are formed on the substrate to cross over at least two of the active regions and the isolation structures, the conductive structures extending in a first direction. An interfacial layer is conformally formed on the substrate in contact with the conductive structures. A first insulation layer is provided on the interfacial layer, wherein the first insulation layer is formed using a flowable chemical vapor deposition (CVD) process, and wherein the interfacial layer reduces a tensile stress generated at an interface between the conductive structures and the first insulation layer while the first insulation layer is formed.


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