The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2014

Filed:

Jun. 20, 2012
Applicants:

Hoon-joo NA, Hwaseong-si, KR;

Hyung-seok Hong, Ansan-si, KR;

Sang-bom Kang, Seoul, KR;

Hyeok-jun Son, Seoul, KR;

June-hee Lee, Hwaseong-si, KR;

Jeong-hee Han, Hwaseong-si, KR;

Sang-jin Hyun, Suwon-si, KR;

Inventors:

Hoon-Joo Na, Hwaseong-si, KR;

Hyung-Seok Hong, Ansan-si, KR;

Sang-Bom Kang, Seoul, KR;

Hyeok-Jun Son, Seoul, KR;

June-Hee Lee, Hwaseong-si, KR;

Jeong-Hee Han, Hwaseong-si, KR;

Sang-Jin Hyun, Suwon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823842 (2013.01); H01L 21/823828 (2013.01); H01L 21/82345 (2013.01);
Abstract

A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.


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