The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2014

Filed:

Jun. 29, 2011
Applicants:

Pieter Van Der Wolf, Leende, NL;

Marc Jeroen Geuzebroek, Budel, NL;

Johannes Boonstra, Deume, NL;

Inventors:

Pieter Van Der Wolf, Leende, NL;

Marc Jeroen Geuzebroek, Budel, NL;

Johannes Boonstra, Deume, NL;

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/16 (2006.01); G06F 13/18 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1605 (2013.01); G06F 13/161 (2013.01); G06F 13/18 (2013.01);
Abstract

Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between origination of an access request from a port of a plurality of ports and a response from the electronic memory. The method also includes calculating a difference between the latency value for the port and a target value associated with the port. The method further includes calculating a running sum of differences for the port covering each of a plurality of access requests. Further, the method includes determining a delta of a priority value for the port based on the running sum of differences. Moreover, the method includes prioritizing the access by the plurality of ports according to associated priority values.


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