The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2014
Filed:
Aug. 28, 2012
Hung Chun Chiu, Fremont, CA (US);
Meng-chyi Lin, Miaoli County, TW;
Kuen-yang Tsai, Hisnchu, TW;
Sweyyan Shei, Cupertino, CA (US);
Hwa Mao, Taipei, TW;
Yingtsai Chang, Fremont, CA (US);
Hung Chun Chiu, Fremont, CA (US);
Meng-Chyi Lin, Miaoli County, TW;
Kuen-Yang Tsai, Hisnchu, TW;
Sweyyan Shei, Cupertino, CA (US);
Hwa Mao, Taipei, TW;
Yingtsai Chang, Fremont, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.