The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2014
Filed:
Feb. 01, 2012
Benjamin J. Bowers, Cary, NC (US);
Matthew W. Baker, Holly Spings, NC (US);
Anthony Correale, Jr., Raleigh, NC (US);
Irfan Rashid, Cary, NC (US);
Paul M. Steinmetz, Holly Springs, NC (US);
Benjamin J. Bowers, Cary, NC (US);
Matthew W. Baker, Holly Spings, NC (US);
Anthony Correale, Jr., Raleigh, NC (US);
Irfan Rashid, Cary, NC (US);
Paul M. Steinmetz, Holly Springs, NC (US);
Mentor Graphics Corporation, Wilsonville, OR (US);
Abstract
Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.