The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2014

Filed:

Jan. 19, 2012
Applicants:

Tadaaki Yoshimura, Tokyo, JP;

Yoji Nishio, Tokyo, JP;

Sadahiro Nonoyama, Toyko, JP;

Koji Matsuo, Tokyo, JP;

Shinji Itano, Tokyo, JP;

Yoshiyuki Yagami, Tokyo, JP;

Inventors:

Tadaaki Yoshimura, Tokyo, JP;

Yoji Nishio, Tokyo, JP;

Sadahiro Nonoyama, Toyko, JP;

Koji Matsuo, Tokyo, JP;

Shinji Itano, Tokyo, JP;

Yoshiyuki Yagami, Tokyo, JP;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 3/06 (2006.01); G06F 5/06 (2006.01); G06F 5/16 (2006.01); G06F 7/78 (2006.01); G06F 9/54 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0656 (2013.01); G06F 2003/0691 (2013.01); G06F 2205/063 (2013.01); G06F 2205/062 (2013.01); G06F 2205/066 (2013.01); G06F 17/50 (2013.01); G06F 5/06 (2013.01); G06F 5/065 (2013.01); G06F 5/16 (2013.01); G06F 7/78 (2013.01); G06F 9/544 (2013.01); G06F 13/1673 (2013.01);
Abstract

A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.


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