The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2014
Filed:
Aug. 29, 2012
Yingtsai Chang, Fremont, CA (US);
Sweyyan Shei, Cupertino, CA (US);
Hung Chun Chiu, Fremont, CA (US);
Hwa Mao, Taipei, TW;
Ming Yang Wang, Lafayette, CA (US);
Yuchin Hsu, Cupertino, CA (US);
Yingtsai Chang, Fremont, CA (US);
Sweyyan Shei, Cupertino, CA (US);
Hung Chun Chiu, Fremont, CA (US);
Hwa Mao, Taipei, TW;
Ming Yang Wang, Lafayette, CA (US);
Yuchin Hsu, Cupertino, CA (US);
Synopsys Taiwan Co., Ltd., Chupei, Hsinchu Hsien, TW;
Synopsys, Inc., Mountain View, CA (US);
Abstract
A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation.