The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2014
Filed:
Mar. 31, 2011
Shunhua T. Chang, South Burlington, VT (US);
Kiran V. Chatty, Williston, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Junjun LI, Williston, VT (US);
Rahul Mishra, Essex Junction, VT (US);
Mujahid Muhammad, Essex Junction, VT (US);
Shunhua T. Chang, South Burlington, VT (US);
Kiran V. Chatty, Williston, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Junjun Li, Williston, VT (US);
Rahul Mishra, Essex Junction, VT (US);
Mujahid Muhammad, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An ESD power clamp circuit and method of ESD protection. The ESD power clamp circuit includes: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network.