The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2014
Filed:
Feb. 16, 2012
Robert L. Maziasz, Austin, TX (US);
Vladimir P. Rozenfeld, Andreevka, RU;
Iouri G. Smirnov, Andreevka, RU;
Alexander V. Zhuravlev, Zelenograd, RU;
Robert L. Maziasz, Austin, TX (US);
Vladimir P. Rozenfeld, Andreevka, RU;
Iouri G. Smirnov, Andreevka, RU;
Alexander V. Zhuravlev, Zelenograd, RU;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A layout tool partially replicates the layout of a base cell to determine the layout for a target cell. The base cell is information representing an arrangement of a set of transistors having an established layout. The target cell is information indicating the desired arrangement of another set of transistors. The layout tool identifies correspondences between subsets of the base cell transistors and subsets of the target cell transistors and replicates the layout of the identified base cell subsets to determine the layout for the identified target cell subsets. In addition, the layout tool can identify base cell subsets that closely match target cell subsets, but for which the layout cannot be exactly replicated because of obstructions in the target cell subsets. For such identified base cell subsets, the layout tool can determine a layout by adjusting the base cell subset layouts to avoid the obstructions.