The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2014

Filed:

Aug. 09, 2010
Applicants:

Kai-ling Chiu, Pingtung County, TW;

Chih-yu Tseng, Hsinchu, TW;

Victor Chiang Liang, Hsinchu, TW;

You-ren Liu, Kaohsiung, TW;

Chih-chen Hsueh, Kaohsiung, TW;

Inventors:

Kai-Ling Chiu, Pingtung County, TW;

Chih-Yu Tseng, Hsinchu, TW;

Victor Chiang Liang, Hsinchu, TW;

You-Ren Liu, Kaohsiung, TW;

Chih-Chen Hsueh, Kaohsiung, TW;

Assignee:

United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.


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