The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2014

Filed:

Nov. 25, 2011
Applicants:

Zen-jay Tsai, Tainan, TW;

Shao-hua Hsu, Taoyuan County, TW;

Chi-horn Pai, Tainan, TW;

Ying-hung Chou, Tainan, TW;

Shih-hao Su, Kaohsiung, TW;

Shih-chieh Hsu, New Taipei, TW;

Chih-ho Wang, Tainan, TW;

Hung-yi Wu, Keelung, TW;

Shui-yen LU, Hsinchu County, TW;

Inventors:

Zen-Jay Tsai, Tainan, TW;

Shao-Hua Hsu, Taoyuan County, TW;

Chi-Horn Pai, Tainan, TW;

Ying-Hung Chou, Tainan, TW;

Shih-Hao Su, Kaohsiung, TW;

Shih-Chieh Hsu, New Taipei, TW;

Chih-Ho Wang, Tainan, TW;

Hung-Yi Wu, Keelung, TW;

Shui-Yen Lu, Hsinchu County, TW;

Assignee:

United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor process is provided. The prior steps include: a first gate including a first cap layer and a second gate including a second cap layer are formed on a substrate. A hard mask layer is formed to cover the first gate and the second gate. The material of the hard mask layer is different from the material of the first cap layer and the second cap layer. The hard mask layer is removed entirely after a lithography process and an etching process are performed. The following steps include: a material is formed to entirely cover the first gate and the second gate. The material, the first gate and the second gate are etched back to make the first gate and the second gate have the same level and expose layers in both of them.


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