The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2014
Filed:
Jul. 31, 2012
Chan-hong Chern, Palo Alto, CA (US);
Tao Wen Chung, San Jose, CA (US);
Ming-chieh Huang, San Jose, CA (US);
Chih-chang Lin, San Jose, CA (US);
Tsung-ching (Jim) Huang, San Jose, CA (US);
Fu-lung Hsueh, Kaohsiung, TW;
Chan-Hong Chern, Palo Alto, CA (US);
Tao Wen Chung, San Jose, CA (US);
Ming-Chieh Huang, San Jose, CA (US);
Chih-Chang Lin, San Jose, CA (US);
Tsung-Ching (Jim) Huang, San Jose, CA (US);
Fu-Lung Hsueh, Kaohsiung, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.