The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 22, 2014
Filed:
Nov. 08, 2012
Lsi Corporation, Milpitas, CA (US);
Pankaj Kumar, Bangalore, IN;
Pramod Parameswaran, Bangalore, IN;
Vani Deshpande, Bangalore, IN;
Makeshwar Kothandaraman, Bangalore, IN;
LSI Corporation, San Jose, CA (US);
Abstract
A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias signals. Magnitudes the first and second bias signals are configured to control a reference signal generated by the reference circuit such that when the reference signal is near a quiescent value of the reference signal, a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the current in the reference circuit increases nonlinearly.