The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 15, 2014
Filed:
Jun. 09, 2011
Chih-chung Wang, Hsinchu, TW;
Wei-lun Hsu, Hsin-Chu Hsien, TW;
Te-yuan Wu, Hsinchu, TW;
Wen-fang Lee, Hsin-Chu, TW;
Ke-feng Lin, Taipei, TW;
Shan-shi Huang, Hsinchu, TW;
Ming-tsung Lee, Yilan County, TW;
Chih-Chung Wang, Hsinchu, TW;
Wei-Lun Hsu, Hsin-Chu Hsien, TW;
Te-Yuan Wu, Hsinchu, TW;
Wen-Fang Lee, Hsin-Chu, TW;
Ke-Feng Lin, Taipei, TW;
Shan-Shi Huang, Hsinchu, TW;
Ming-Tsung Lee, Yilan County, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.