The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 15, 2014
Filed:
Feb. 13, 2012
Toshiharu Furukawa, Essex Junction, VT (US);
Steven J. Holmes, Guilderland, NY (US);
David V. Horak, Essex Junction, VT (US);
Charles W. Koburger, Iii, Delmar, NY (US);
Toshiharu Furukawa, Essex Junction, VT (US);
Steven J. Holmes, Guilderland, NY (US);
David V. Horak, Essex Junction, VT (US);
Charles W. Koburger, III, Delmar, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile