The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2014
Filed:
Dec. 30, 2010
Prakash Gopalakrishnan, Wayne, NJ (US);
Michael Mcsherry, Portland, OR (US);
David White, San Jose, CA (US);
Ed Fischer, Salem, OR (US);
Bruce Yanagida, Snohomish, WA (US);
Keith Dennison, Edinburgh, GB;
Prakash Gopalakrishnan, Wayne, NJ (US);
Michael McSherry, Portland, OR (US);
David White, San Jose, CA (US);
Ed Fischer, Salem, OR (US);
Bruce Yanagida, Snohomish, WA (US);
Keith Dennison, Edinburgh, GB;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.