The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2014

Filed:

Jan. 13, 2012
Applicants:

Masaru Yano, Tokyo, JP;

Lu-ping Chiang, Hsinchu, TW;

Inventors:

Masaru Yano, Tokyo, JP;

Lu-Ping Chiang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory device includes a memory array, a row selection circuit and a bit line selection circuit. The memory array is composed of a plurality of cell units, wherein each cell unit has memory cells connected in series. The row selection circuit selects the memory cells in a row direction of the cell units, and the bit line selection circuit selects a bit line from an even bit line and an odd bit line coupled to the cell units. The bit line selection circuit includes a first selection part including selection transistors for selectively coupling the even or odd bit line to a sensor circuit and a second selection part including bias transistors for selectively coupling the even or odd bit line to a voltage source providing biases, wherein the bias transistors and the memory cells are formed in a common well.


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