The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2014
Filed:
Jul. 15, 2011
Fang-shi Jordan Lai, Chia Yi, TW;
Chih-cheng LU, Tainan, TW;
Yung-fu Lin, Hsinchu, TW;
Hsu-feng Hsueh, Tainan, TW;
Chin-hao Chang, Hsinchu, TW;
Cheng Yen Weng, Hsinchu, TW;
Manoj M. Mhala, Hsinchu, TW;
Fang-Shi Jordan Lai, Chia Yi, TW;
Chih-Cheng Lu, Tainan, TW;
Yung-Fu Lin, Hsinchu, TW;
Hsu-Feng Hsueh, Tainan, TW;
Chin-Hao Chang, Hsinchu, TW;
Cheng Yen Weng, Hsinchu, TW;
Manoj M. Mhala, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.