The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2014

Filed:

Jul. 24, 2013
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chun-Mao Chiou, Chiayi County, TW;

Ti-Bin Chen, Tainan, TW;

Tsung-Min Kuo, Tainan, TW;

Shyan-Liang Chou, Tainan, TW;

Yao-Chang Wang, Tainan, TW;

Chi-Sheng Tseng, Tainan, TW;

Jie-Ning Yang, Ping-Tung County, TW;

Po-Jui Liao, Taichung, TW;

Assignee:

United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.


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