The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2014
Filed:
Jul. 27, 2009
Holger Klingner, Erfurt, DE;
Jens Ungelenk, Bad Berka, DE;
Holger Klingner, Erfurt, DE;
Jens Ungelenk, Bad Berka, DE;
X-Fab Semiconductor Foundries AG, Erfurt, DE;
Abstract
A method for aligning an electronic CMOS structure with respect to a buried structure in the case of a bonded and thinned back stack of semiconductor wafers. The method for aligning the electronic CMOS structure may include forming alignment marks in the process of fabricating the structure to be buried on a front side, which is used for bonding of the semiconductor wafer, which includes the structure to be buried. The alignment marks may be formed on the edge of the semiconductor wafer. The method for aligning the electronic CMOS structure may include providing a cover wafer with first thinned portions of the wafer thickness provided from the bonding side at positions corresponding to positions of the alignment marks. After the thinning of the cover wafer a plan view of the alignment mark is obtained after the wafer bonding that initially results in a burying of the structures, wherein subsequently the resulting wafer stack is thinned to a certain degree with respect to the cover wafer, thereby making visible the at least one alignment mark, and by means of the alignment mark masks of method steps for fabricating the electronic structure on the surface of the thinned cover wafer are aligned.