The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2014
Filed:
Jun. 24, 2011
Igor Polishchuk, Fremont, CA (US);
Sagy Levy, Zichron Ya'aqov, IL;
Krishnaswamy Ramkumar, San Jose, CA (US);
Jeong Soo Byun, Cupertino, CA (US);
Igor Polishchuk, Fremont, CA (US);
Sagy Levy, Zichron Ya'aqov, IL;
Krishnaswamy Ramkumar, San Jose, CA (US);
Jeong Soo Byun, Cupertino, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
Non-volatile semiconductor memories and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method includes: (i) forming a gate for a non-volatile memory transistor on a surface of a substrate overlaying a channel region formed therein, the gate including a charge trapping layer; and (ii) forming a strain inducing structure over the gate of the non-volatile memory transistor to increase charge retention of the charge trapping layer. Preferably, the memory transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) transistor comprising a SONOS gate stack. More preferably, the memory also includes a logic transistor on the substrate, and the step of forming a strain inducing structure comprises the step of forming the strain inducing structure over the logic transistor. Other embodiments are also disclosed.