The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2014

Filed:

Oct. 02, 2011
Applicants:

Deepak C Sekar, San Jose, CA (US);

Zvi Or-bach, San Jose, CA (US);

Paul Lim, Monte Sereno, CA (US);

Inventors:

Deepak C Sekar, San Jose, CA (US);

Zvi Or-Bach, San Jose, CA (US);

Paul Lim, Monte Sereno, CA (US);

Assignee:

Monolithic 3D Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

An Integrated device comprising a first monocrystalline layer comprising logic circuit regions and a second monocrystalline layer comprising memory regions constructed above first monocrystalline layer, wherein the memory regions comprise second transistors, wherein said second transistors comprise drain and source that are horizontally oriented with respect to the second monocrystalline layer, and a multiplicity of vias through the second monocrystalline layer providing connections between the memory regions and the logic circuit regions, wherein at least one of the multiplicity of vias have a radius of less than 100 nm.


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