The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2014
Filed:
Dec. 20, 2012
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Fulong Zhang, Cupertino, CA (US);
Chien Kuang Chen, San Jose, CA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
A margin circuit for controlling skew between first and second signals in order to determine margin, includes a variable delay circuit and a margin controller. Based on a current code value, the delay circuit applies a delay to the second signal to generate a delayed second signal. The margin controller generates the current code value for the variable delay circuit to be any one of a plurality of available code values. In one embodiment, the margin circuit is a write margin circuit that generates a first clock signal and a delayed second clock signal used to generate transmit (TX) clock and data signals having a non-zero phase offset between them. In another embodiment, the margin circuit is a read margin circuit that applies a phase offset between receive (RX) clock and data signals to enable the RX clock signal to be used to recover data from the RX data signal.