The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2014
Filed:
Apr. 07, 2010
Pirooz Parvarandeh, Los Altos Hills, CA (US);
Reynante Alvarado, San Jose, CA (US);
Chiung C. Lo, Campbell, CA (US);
Arkadii V. Samoilov, Saratoga, CA (US);
Pirooz Parvarandeh, Los Altos Hills, CA (US);
Reynante Alvarado, San Jose, CA (US);
Chiung C. Lo, Campbell, CA (US);
Arkadii V. Samoilov, Saratoga, CA (US);
Maxim Integrated Products, Inc., San Jose, CA (US);
Abstract
Wafer-level chip-scale package semiconductor devices are described that have bump assemblies configured to mitigate solder bump failures due to stresses, particularly stresses caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having two or more arrays of bump assemblies for mounting the device to a printed circuit board. At least one of the arrays includes bump assemblies that are configured to withstand higher levels of stress than the bump assemblies of the remaining arrays.