The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2014
Filed:
Nov. 30, 2012
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Mitchell W Hines, San Jose, CA (US);
Chung-Fu Chang, San Jose, CA (US);
Reuber Duarte, Campbell, CA (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method is provided to test an integrated circuit design for power management circuit design errors comprising: configuring a computer to identify multiple power domain crossing paths between pairs of power domains; identify one or more power related constraints associated with such power domain crossing paths; and group power domain crossing paths between matching power domain pairs that are associated with matching power related constraints.