The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2014
Filed:
Jan. 27, 2012
Deepak Mital, Orefield, PA (US);
William Burroughs, Macungie, PA (US);
David Sonnier, Austin, TX (US);
Steven Pollock, Allentown, PA (US);
David Brown, Austin, TX (US);
Joseph Hasting, Orefield, PA (US);
Deepak Mital, Orefield, PA (US);
William Burroughs, Macungie, PA (US);
David Sonnier, Austin, TX (US);
Steven Pollock, Allentown, PA (US);
David Brown, Austin, TX (US);
Joseph Hasting, Orefield, PA (US);
LSI Corporation, Milpitas, CA (US);
Abstract
Described embodiments provide a network processor having a plurality of processing modules coupled to a system cache and a shared memory. A memory manager allocates blocks of the shared memory to a requesting one of the processing modules. The allocated blocks store data corresponding to packets received by the network processor. The memory manager maintains a reference count for each allocated memory block indicating a number of processing modules accessing the block. One of the processing modules reads the data stored in the allocated memory blocks, stores the read data to corresponding entries of the system cache and operates on the data stored in the system cache. Upon completion of operation on the data, the processing module requests to decrement the reference count of each memory block. Based on the reference count, the memory manager invalidates the entries of the system cache and deallocates the memory blocks.